Bipolar transistors are electronic devices with two p-n junctions that are in close proximity to each other. A typical bipolar transistor has three device regions: an emitter, a collector, and a base disposed between the emitter and the collector. Ideally, the two p-n junctions, i.e., the emitter-base and collector-base junctions, are in a single layer of semiconductor material separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called “bipolar-transistor action.”
If the emitter and collector are doped n-type and the base is doped p-type, the device is an “npn” transistor. Alternatively, if the opposite doping configuration is used, the device is a “pnp” transistor. Because the mobility of minority carriers, i.e., electrons, in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn transistor devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
As the vertical dimensions of the bipolar transistor are scaled more and more, serious device operational limitations have been encountered. One actively studied approach to overcome these limitations is to build transistors with emitter materials whose band gaps are larger than the band gaps of the material used in the base. Such structures are called heterojunction transistors.
Heterostructures comprising heterojunctions can be used for both majority carrier and minority carrier devices. Among majority carrier devices, heterojunction bipolar transistors (HBTs) in which the emitter is formed of silicon (Si) and the base of a silicon-germanium (SiGe) alloy have recently been developed. The SiGe alloy (often expressed simply as silicon-germanium) is narrower in band gap than silicon.
The advanced silicon-germanium bipolar and complementary metal oxide semiconductor (BiCMOS) technology uses a SiGe base in the heterojunction bipolar transistor. In the high-frequency (such as multi-GHz) regime, conventional compound semiconductors such as GaAs and InP currently dominate the market for high-speed wired and wireless communications. SiGe BiCMOS promises not only a comparable performance to GaAs in devices such as power amplifiers, but also a substantial cost reduction due to the integration of heterojunction bipolar transistors with standard CMOS, yielding the so-called “system on a chip.”
For high-performance HBT fabrication, yielding SiGe/Si HBTs, a conventional way to reduce the base resistance is through ion implantation into the extrinsic base. The ion implantation will cause damage, however, to the base region. Such damage may ultimately lead to degradation in device performance.
To avoid the implantation damage, a raised extrinsic base (Rext) is formed by depositing an extra layer of polycrystalline silicon (or SiGe) atop the conventional SiGe extrinsic base layer. There are essentially two processes that may be utilized to achieve such a raised extrinsic base. The first process involves selective epitaxy; the other involves chemical-mechanical polishing (CMP).
In a typical selective epitaxy process, the raised extrinsic base polycrystalline silicon is formed before the deposition of the intrinsic base SiGe. The intrinsic base SiGe is deposited selectively onto the exposed surface of silicon and polycrystalline silicon inside an over-hanging cavity structure. The selective epitaxy with a cavity structure mandates stringent process requirements for good selectivity, and suffers from poor process control. U.S. Pat. No. 5,523,606 to Yamazaki and U.S. Pat. No. 5,620,908 to Inoh, et al. are some examples of prior art selective epitaxy processes.
As mentioned above, CMP can be applied to form a raised extrinsic base. U.S. Pat. No. 5,015,594 to Chu et al. discloses the formation of extrinsic base polysilicon by CMP. The isolation, which is achieved by thermal oxidation, is not feasible in high performance devices due to the high temperature thermal process.
U.S. Pat. No. 6,492,238 to Ahlgren, et al. provides a self-aligned process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a complementary metal oxide semiconductor (CMOS) circuit with a gate. An intermediate semiconductor structure is provided having a CMOS area and a bipolar area. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack of silicon layer is deposited on both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the emitter stack silicon layer from the CMOS area only such that the top surface of the emitter stack silicon layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP).
Despite being capable of forming an HBT having a raised extrinsic base, the self-aligned-CMP process disclosed in the '238 patent is complicated requiring many different processing steps to achieve the desired structure. As such, there still exists a need for providing a simple and reliable method for fabricating high-performance HBTs that have a raised extrinsic base.